One of the most important advances in the area of electronic integrated circuit (IC) design over the past few years has been the development of logic synthesis as part of the overall IC design process. In a nutshell, logic synthesis allows IC designers to more fully utilize the ever-increasing number of transistors available in an IC while ignoring the tedious complexities associated with direct gate-level design. Thus, logic synthesis has allowed the designer to concentrate on the functionality of an IC while, at the same time, reducing its associated time-to-market.
As shown in FIG. 1, logic synthesis currently is a vital part of a typical IC design process 1. An IC designer initially generates a high-level behavioral or register-transfer-level (RTL) description (step 100) of the functionality of a proposed IC, which is normally written in a hardware design language (HDL), with VHDL and Verilog being the two most popular examples. Often, a functional simulation of the behavioral or RTL description is performed thereafter to determine if the circuit logically operates as was intended (step 110). If this simulation (step 110) yields no unpleasant surprises, the designer then uses a set of software tools that performs logic synthesis (step 120) to transform the behavioral or RTL description into a schematic representation of circuit elements, such as logic gates, transistors, resistors, and the like, along with the associated logical connections between elements. The synthesized circuit elements and logical connections are then simulated once again (step 130) at the logic gate level to check the operation of the circuit against previously specified voltage and timing constraints. If the gate-level simulation (step 130) executes successfully, the schematic of circuit elements and connections is then passed to a xe2x80x9cplace-and-routexe2x80x9d tool (step 140), which determines the actual location of the circuit elements and connections within the space available on the IC. A final simulation (step 150) is then performed, this time on the circuit generated by the place-and-route tool, in order to determine if the chip meets all functional and timing constraints, given the actual physical layout of the circuit.
As can be seen in FIG. 1, successful completion of a step of the IC design process brings the IC design one step closer to being a viable IC. Conversely, any problems or failures discovered in any of the steps results in some portion of the design process to be repeated. (FIG. 1 indicates a few of the possible xe2x80x9crepeatingxe2x80x9d paths.) In the past, a reasonable number of failures were expected early on in the process, such as during functional simulation (step 110) or gate-level simulation (step 130), with relatively few problems encountered at final simulation (step 150).
However, with the decreasing size in the IC geometries being used, and the correspondingly higher number of transistors available on an IC, the standard design process described above has proven inadequate at times, with a significant number of IC failures not being discovered until final simulation (step 150). This is especially problematic considering that the manufacturing process for the IC is oftentimes begun prior to final simulation, since that simulation (step 150) is quite a time-consuming task due to the complex nature of the circuit models and current waveforms involved. Unlike before, when logic gate timing delays contributed the overwhelming majority of the overall timing delay of a signal, the latest advances in IC manufacturing technology have caused the connections between logic gates to be the single largest contributor to signal delay in most cases. Since the signal delay in a connection is dependent upon the length of that connection, the placement and routing of the connection must be known with a high degree of certainty in order to accurately model the signal delay involved. Unfortunately, under typical IC design process 1, the place-and-route information is not known until well after the RTL design and synthesis steps have been performed.
Recently, companies such as Synopsis Inc. and Avant! Corporation have devised new IC design tool strategies to deal with this problem. Although the various strategies differ in the details, they basically involve the addition of xe2x80x9cquick,xe2x80x9d or non-final, types of synthesis and place-and-route functions earlier in the design process to determine within certain error limits the lengths of the interconnections in the IC. In FIG. 2, an updated IC design process 2 is shown, with a quick synthesis and place-and-route step (step 200) essentially being added early in the design flow. (Frequently, the xe2x80x9cquickxe2x80x9d place-and-route function is termed xe2x80x9cfloorplanningxe2x80x9d.) As a result, timing simulations at the gate level are carried out using preliminary physical layout information, thereby giving the IC designer greater confidence that the IC will actually perform as expected prior to final place-and-route. In other words, the xe2x80x9clogicalxe2x80x9d design steps of RTL definition and logic synthesis are more tightly coupled with the xe2x80x9cphysicalxe2x80x9d design steps of placing and routing under updated IC design process 2. Potential timing problems are thus discovered earlier in the design process, saving development time that would otherwise be wasted during place-and-route (step 140) and final simulation (step 150). Therefore, the problems involved with meeting timing constraints under the older process have been mitigated somewhat with the newer IC design approaches.
However, the latest advances in design methodology do not appear to address all of the problems associated with the typical separation of the logical and physical portions of IC design. For example, some currently available IC design tools allow analysis of the average magnitude of the loads placed on the on-chip power grid during the logical portion of the design cycle to determine power requirements for the various areas of the IC. However, the IC power supply circuitry, which includes both the on-chip power circuitry and the IC package power circuitry, is generally not taken into account during the design of the IC core logic. As a result, incompatibilities between the IC power supply circuitry and the IC core logic circuitry can cause problems not easily identified until final simulation (step 150).
Even if fluctuations of the power supply at the pins of an IC package are insignificant, the power still has a significant amount of circuitry to traverse before it reaches the on-chip logic circuitry of an IC, as can be seen in the diagrammatic representation of FIG. 3. More specifically, package power supply pins 320, typically labeled VDD and GND, are the entry points of the power and ground connections into an IC package 300. Ordinarily, on LSI components, multiple VDD and GND power supply pins 320 are supplied to allow a sufficient amount of current to pass between IC package 300 and a circuit board power supply circuit 310 to operate the chip properly. Power supply pins 320 are, in turn, connected to a package power supply circuit 330, which is made up primarily of, but not limited to, a network of metal planes, grids, and bypass capacitors inside the IC package. Package power supply circuit 330, in turn, provides power to an on-chip power supply circuit 340, which is made up mainly of metal grids and more bypass capacitors. It is on-chip power supply circuit 340 that is attached via multiple connection points to an IC core logic circuit 350, which performs the logical functions expected of the IC. As is well-known in the art, the bypass capacitors in package power supply circuit 330 and on-chip power supply circuit 340 are placed across the power and ground planes and grids to help stabilize the power supply voltage levels by providing charge during short time periods of high current demand by core logic circuit 350.
As can be appreciated by someone of skill in the art, the IC designer pays much attention to the problem of providing adequate and stable power to core logic circuit 350 by investing a significant amount of time and resources into the design of both package power supply circuit 330 and on-chip power supply circuit 340. However, depending on the physical and operational characteristics of core logic circuit 350, problems in the power supplied at the core may still exist, leading to faults in the operation of the logic circuitry. For example, package power supply circuit 330, with its network of planes, grids, and bypass capacitors, usually exhibits a resonant frequency at which the impedance of that circuitry increases substantially. If at least some portion of core logic circuit 350 is operated in a periodic fashion at or near that resonant frequency, package power supply circuit 330 will exhibit the increased impedance, thereby resulting in a reduced power supply voltage at core logic circuit 350 during that time. Such an unstable power supply voltage, in turn, causes the voltage trigger points of core logic circuit 350 to fall, possibly allowing small amounts of noise on a signal line to trigger a logic gate input falsely, thereby causing operational failure of the IC. On-chip or externally provided clock signals are typical determinants of the operational frequency of the clock. However, even clock signals with primary frequencies less than that of the resonant frequency of the IC package may cause problems, since many harmonics are present in such clock signals, especially those clock signals with extremely short rise and falls times. Oppositely, clock signal frequencies greater than the package resonant frequency may also cause failures, as some large portions of core logic circuit 350 may trigger in response to multiple periods of a clock signal, resulting in operational frequencies that are some fraction of that of the original clock signal.
Package power supply circuit 330 is not the only source of power supply impedance. On-chip power supply circuit 340, with its power supply grid and bypass capacitors on the IC chip itself, also contributes to this effect, often generating a more prominent resonance point at a higher frequency than its package counterpart. With two resonance points in the power supply circuit, it can be appreciated by those skilled in the art that the power supply resonances are potential barriers to designing a chip that works correctly for all combinations of temperature, timing, and supply voltage constraints that are specified for the IC.
In addition to the periodic nature of core logic circuit 350, and its interaction with the resonant frequencies of package and on-chip power supply circuits 330 and 340, core logic circuit 350 may also exhibit substantial non-periodic current demands on the power supply circuitry in the form of current xe2x80x9cspikes,xe2x80x9d or short, non-periodic instances of extremely high current demand. These spikes occur, for example, as a result of the response of core logic circuit 350 to a change in state of one of the IC input signal lines driven by circuitry external to IC package 300. Logic signal changes within IC package 300 may also cause current spikes to occur. Spikes of sufficiently large magnitude cause temporary failure in the portion of the power supply circuitry that is in close proximity to the section of core logic circuit 350 responsible for that current demand. Unfortunately, in order to detect such problems prior to final simulation 150, more information concerning the structure of package and on-chip power supply circuits 330 and 340 is required earlier in IC design processes 1 and 2. For example, the nature of the power supply circuitry must be known sufficiently to determine the level of current demand necessary at various locations within core logic circuit 350 to cause a drop in supply voltage that would cause core logic circuit 350 to fail.
Unfortunately, the electrical characteristics of the package and on-chip power supply circuits, including the identity of the power supply circuit resonant frequencies, and their resultant effects on the operation of core logic circuit 350, are currently not known with sufficient accuracy during the logic description (100) and synthesis (120) steps of either of design processes 1 and 2 described above to prevent design problems early in the IC design cycle. Typically, such problems are not found until final simulation, which is rather late in the design process, impacting time-to-market adversely.
Thus, it would be advantageous to utilize information concerning the power supply circuitry of the package and the chip earlier in the IC design cycle to modify the synthesis of the IC core logic. Such modification would help avoid operational faults related to the periodic and non-periodic interaction of the core logic and the power supply circuitry.
The embodiments of the invention, to be discussed in detail below, allow the use of the package and on-chip chip power supply circuit models and associated resonant frequencies as input to the initial IC RTL description and synthesis process. These additional inputs, when used properly, help prevent the core logic from placing too high a periodic current demand at the resonant frequencies, and too high a non-periodic current spike that exceeds the capabilities of the package and on-chip power supply circuits. Without specific information concerning the electrical characteristics of the power supply circuits, valuable time-to-market is often wasted during the initial description, synthesis, and simulation of the IC in creating a logic core that is incompatible with the power supply circuitry that will be used to drive the chip.
According to an embodiment of the invention, a method of adjusting the core logic of an IC based on the electrical characteristics of the package and on-chip power supply circuits begins with developing electrical models of those power supply circuits. As will be discussed later, on-chip power supply SPICE models for ICs recently have become available prior to initial floorplanning activity. Similarly, package power supply circuitry for a particular package size is also available, with the associated SPICE model. Circuit simulations are then performed on each of these two models in order to determine the primary resonant frequencies identified with each of the power supply circuits. The resonant frequency of the on-chip power supply circuit is then used as input to initial floorplanning, or xe2x80x9cfirst chip route,xe2x80x9d for the IC. Positional current waveforms, each specific to various locations on the IC core logic, are then developed from an analysis of the initial floorplan. The positional current waveforms are, in turn, used in conjunction with the previously generated power supply circuit models to run power supply integrity simulations. The results of these power supply integrity simulations, along with the two previously identified resonant frequencies, are then used to generate design constraints associated with the power supply circuitry and its interaction with the core logic circuitry. The design constraints are then used to either manually modify the core logic by way of the RTL description language, or to automatically modify the logic synthesis process. Whether the manual or automatic approach is taken, the core logic of the IC is modified according to techniques known in the art so that the primary frequency components of the electrical current demands of the logic are xe2x80x9cpushed awayxe2x80x9d from those resonant frequencies. Also, problematic core logic current waveforms are also xe2x80x9csmoothed outxe2x80x9d so that the magnitude of current frequencies coinciding with the resonant frequencies, and the magnitude of non-periodic current demands, are reduced to a level that will not cause power supply voltage failures.
In some cases, either the package or on-chip power supply circuit model is not obtained before the RTL description of the core logic circuit has been synthesized. Embodiments of the invention exist which allow the model of either the package or on-chip power supply circuit to be utilized for adjustment of the core logic gate-level description.
Another embodiment of the invention is a system which produces a set of design constraints that mitigate problems associated with the interaction of the package and on-chip power supply circuits and the core logic circuit. One portion of the system is a circuit simulator, which takes the package and on-chip power supply circuit models as input, and determines the primary resonant frequencies for those models. Also included in the system is an initial floorplanner, which takes as input the on-chip power supply resonant frequency and the initial block-level description of the core logic circuit as input, and generates a set of positional current waveforms. A power supply integrity simulator then utilizes the positional waveforms and the power supply circuit models to generate a set of design constraints associated with the power supply circuits. The design constraints, in addition to the identity of the power supply resonant frequencies, are then either used as input to a logic synthesis tool to adjust the synthesis of the core logic circuit, or used manually by an IC designer to adjust the high-level description of the core logic.
Additionally, alternate system embodiments allow the use of either the package or on-chip power supply circuit model alone, thus allowing the absence of one of the power supply circuit models while adjusting the IC core logic using information about the known power supply circuit model.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.